In recent years, to meet the need to reduce the size and the thickness of electronic equipment, there have been developed semiconductor assemblies with bare semiconductor devices directly mounted on a wiring board. One such type of semiconductor assembly employs “flip-chip mounting” technology.
The “flip-chip mounting” technology is one of the methods for mounting the semiconductor device (chip) on the wiring board, in which projecting terminals called bumps are provided and arranged in a matrix on one principal surface of the planar semiconductor device, and the terminals are connected to electrodes provided in the wiring board. Hereinafter, a semiconductor assembly employing “flip-chip mounting” will be referred to as a “flip-chip-type” semiconductor assembly, and such a connection method will be referred to as “flip-chip bonding”.
The flip-chip-type semiconductor assembly has a reduced mounting area compared to semiconductor assemblies employing wire bonding. Also, short wiring advantageously provides satisfactory electrical characteristics.
In the flip-chip-type semiconductor assembly, semiconductor devices are typically mounted on a multilayer wiring board. The wiring board has wiring patterns formed on two principal surfaces, and the wiring patterns are electrically connected to each other through vias formed in the wiring board. One of the two wiring patterns is connected to internal connection terminals (bumps) of the semiconductor devices, while the other is connected to external connection terminals such as solder balls. Also, thermo-setting resin, such as epoxy resin, is injected between the semiconductor devices and the wiring board, thereby protecting the internal connection terminals.
FIG. 13 illustrates an exemplary structure of a conventional flip-chip-type semiconductor assembly SAP. Also, FIG. 14 illustrates the structure of a multilayer wiring board MBP used in the semiconductor assembly SAP. As shown in FIG. 13, the semiconductor assembly SAP has a semiconductor device SD mounted on one of the principal surfaces of the multilayer wiring board MBP.
As shown in FIG. 14, the multilayer wiring board MBP has insulating layers 3 and 4 laminated on two principal surfaces of an insulating layer (hereinafter, referred to as a “core board”) 1 disposed in the middle. The insulating layer 3 is disposed on the flip-chip bonding side with respect to the core board 1, while the insulating layer 4 is disposed on the opposite side to the flip-chip bonding side with respect to the core board 1.
Wire conductors 5 for connection with the semiconductor device SD are provided on the surface (top surface in FIG. 14) of the insulating layer 3. On the other hand, secondary mounting terminal electrodes 8 are provided on the surface (bottom surface in FIG. 14) of the insulating layer 4. The secondary mounting terminal electrodes 8 are used for secondary mounting of the semiconductor assembly SAP onto an unillustrated motherboard. Solder resists 7 are applied between the secondary mounting terminal electrodes 8 in order to avoid short-circuit between adjacent electrodes at the time of the connection with the wire conductors of the motherboard by soldering or suchlike.
Interlayer electrodes 9 are provided between the insulating layer 3 and the core board 1 and between the core board 1 and the insulating layer 4. Also, vias 6 are provided in the insulating layer 3, the core board 1, and the insulating layer 4, so that the wire conductors 5 and the secondary mounting terminal electrodes 8 are electrically connected through the interlayer electrodes 9 and the vias 6.
As shown in FIG. 13, the semiconductor device SD consists of a main element portion 20, electrode pads 21, and bumps 22. The electrode pads 21 are provided on one surface (bottom surface in FIG. 13) of the planar main element portion 20, and the electrode pads 21 are provided with their respective bumps 22. Also, thermo-setting sealing resin 23 is injected between the semiconductor device SD and the multilayer wiring board MBP.
When the sealing resin 23 is cured with the bumps 22 of the semiconductor device SD being pressed hard on the wire conductors 5 of the multilayer wiring board MBP, the semiconductor device SD is fixed to the multilayer wiring board MBP with the bumps 22 in close contact with the wire conductors 5, so that the semiconductor device SD and the multilayer wiring board MBP are electrically connected.
Referring next to FIG. 13, the process for flip-chip mounting the semiconductor device SD onto the multilayer wiring board MBP and warpage of the multilayer wiring board MBP that is produced due to the process will be described.
A prepared multilayer wiring board MBP is placed on an unillustrated metallic stage. Then, a semiconductor device SD is placed on the multilayer wiring board MBP such that uncured sealing resin 23 is positioned between the semiconductor device and the multilayer wiring board MBP, and bumps 21 face wire conductors 5.
Furthermore, an unillustrated heat tool is placed on the semiconductor device SD, and heated while being pressed hard on the semiconductor device SD. The applied pressure deforms the tips of the bumps 22 to such an extent as to achieve satisfactory connections with the wire conductors 5, and the heat applied by the heat tool cures the sealing resin 23, thereby maintaining this state.
When mounting the semiconductor device SD on the multilayer wiring board MBP, the multilayer wiring board MBP and the semiconductor device SD are pressed between the stage and the heat tool, and heated at a temperature of approximately 180° C. The heating horizontally expands the core board 1 and the insulating layers 2, 3, and 4 included in the multilayer wiring board MBP.
After the sealing resin 23 is cured for a predetermined period of time (5 to 10 seconds), the heat and the pressure applied to the heat tool are removed. The core board 1 and the insulating layers 3 and 4 that have expanded horizontally contract as the temperature falls. At this time, the insulating layer 3, which lies at the top, is firmly bonded to the semiconductor device SD via the sealing resin 23.
The thermal expansion coefficient of the semiconductor device SD is considerably lower than that of the insulating layer 3, and therefore the semiconductor device SD prevents contraction of the insulating layer 3. The amounts of contraction of the core board 1 and the insulating layers 2, 3, and 4 are as indicated by horizontal arrows in FIG. 13, and as a result, force is applied to both ends in the directions indicated by arrows C1 and C2, so that the multilayer wiring board MBP is convexly warped.
While the semiconductor assembly SAP thus produced is thereafter mounted on a motherboard, high warpage of the multilayer wiring board MBP reduces the reliability of connecting the secondary mounting terminal electrodes 8 to the wire conductors of the motherboard by soldering.
Patent Document 1 proposes methods for preventing warpage of the multilayer wiring board having the semiconductor device mounted thereon: (1) the multilayer wiring board includes insulating layers of resin materials with different elasticity or thermal expansion coefficients; (2) the insulating layers differ in thickness; and (3) the insulating layers differ in glass cloth content.    Patent Document 1 Japanese Laid-Open Patent Publication No. 2001-217514